1. Field of the Invention
The present invention relates to a method for determining an operating voltage of floating point error detection of a central processing unit (CPU), and more specifically, the present invention discloses a method for determining an operating voltage of floating point error detection of a CPU via a south bridge chipset.
2. Description of the Prior Art
With the rapid development of computers, development of CPU technology has become important. Computers with Intel x86 architecture used to require floating point co-processors (math co-processors) to effectively perform floating point calculations. More recently, manufacturers have embedded floating point units (FPU) into their CPUs, thereby increasing floating point calculation speed substantially. Currently, many CPUs on the market use this concept to deliver high processing speeds.
In a typical computer system there are two types of numerical data, integers and floating point numbers. Storing an integer in a computer system is relatively simple, but a floating point number must be represented as an integer part, a fractional part, and an exponent. One can appreciate the methods of performing calculations on an integer and floating point number are quite different, with floating point operations being much more complicated.
The processing speed of today's CPUs has reached the gigahertz level and the latest software uses this potential to the fullest. For example, animation software that performs rendering and texture mapping functions needs to execute a large number of floating point calculations during a short period. With this high rate of floating point calculations comes the risk of floating point errors in the FPU. If an error does occur, the CPU will indicate such by a floating point error signal (FERR#) that is sent to a south bridge chipset on the motherboard for further processing.
In order for the south bridge chipset to correctly interpret the FERR# and properly recognize that a floating point error has occurred, the south bridge chipset must first establish the operating voltage of the floating point error. In practical application, the operating voltage of the floating point error is the operating voltage of the CPU. Now suppose that the operating voltage of the CPU is 2 volts. That is, the FERR# output by the CPU will be between 0 and 2 volts. If the FERR# accepted by the south bridge chipset is greater than 1 volt, a corresponding binary digital value represented by the FERR# is “1”. Similarly, if the FERR# accepted by the south bridge chipset is smaller than 1 volt, the corresponding binary digital value represented by the FERR# is “0”.
It is often the case that CPUs of the same manufacturer have different operating voltages. For example, an Intel Pentium II processor operates at 1.5 volts yet an Intel Pentium III processor runs at 2.5 volts. As the south bridge chipset requires the operating voltage of the floating point error to correctly interpret FERR#, the south bridge chipset needs to first determine the operating voltage of the CPU.
Please refer to FIG. 1. FIG. 1 is a flow chart that describes setting an operating voltage of floating point error detection according to the prior art.
Step 101: a basic input/output system (BIOS) accesses identification data of the CPU;
Step 102:the BIOS determines an operating voltage of the CPU based on the identification data of the CPU;
Step 103: is the operating voltage of the CPU 1.5 volts? if so, go to step 104; if not, go to step 105;
Step 104: the operating voltage of floating point error detection is 1.5 volts;
Step 105: the operating voltage of floating point error detection is 2.5 volts.
As shown above, the BIOS is an essential element in determining the operating voltage of floating point error detection of the CPU. If the BIOS malfunctions or otherwise introduces an error into the system, the operating voltage of floating point error detection will not be correctly determined. To avoid errors, manufacturers must currently ensure compatibility by testing BIOS systems with the wide array of CPUs available and their numerous identification data and operating voltages.